Instruction set enhancements for reliable computations
Michael Schulte, Ahmet Akkaş · 2001
Although there have been significant advances in VLSI technology and numerical computing, floating-point computations still suffer from undetected errors due to rounding and catastrophic cancellation. Fast computers let programmers write numerically intensive programs, but computed results can be far from the true results due to the accumulation of errors in arithmetic operations. Therefore, accurate and reliable computations have become more important. Interval arithmetic is one technique for accurate and reliable computing. With interval arithmetic, each data value is represented by two floating-point numbers which correspond to the endpoints of an interval, such that the true result is guaranteed to lie on this interval. Since interval arithmetic represents ranges of numbers, it also provides the ability to solve problems that cannot be efficiently solved using floating-point arithmetic. Although interval arithmetic provides an efficient method for monitoring and controlling errors in floating-point computations, it is not yet used widely because it is not sufficiently fast. This dissertation investigates instruction set enhancements for interval arithmetic. Existing interval arithmetic programs are examined to determine bottlenecks in interval computations. Then, a variety of instruction set enhancements are pro posed to overcome these bottlenecks. The efficiency of the proposed enhancements are evaluated using an interval-enhanced compiler and a superscalar processor simulator. Hardware modifications to support these enhancements are evaluated, and a novel design for a combined Interval and Floating-point Comparator is presented. This dissertation also investigates instruction set enhancements for extended precision arithmetic. In particular, instruction set support for quadruple precision arithmetic is examined. Hardware modifications needed to support quadruple precision arithmetic on superscalar processor is evaluated to determine which extensions can be most efficiently incorporated into superscalar processor designs. Furthermore, a technique for performing parallel double precision multiplication using quadruple precision hardware is proposed.