Reducing computation delay of Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm by using CSA
G Ramya Sudha, Ch. Manohar · IOSR Journal of VLSI and Signal processing · 2014
In this paper, our main focus is to reduce computation delay proposed in previous FFA algorithm based FIR digital filter.Parallel FIR filter structure with fast finite-impulse response (FIR) along with symmetric coefficients reduces the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. .The proposed parallel FIR structures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in sub filter section at the expense of additional adders in preprocessing and post processing blocks.Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area; in addition, the overhead from the additional adders in preprocessing and post processing blocks stay fixed and do not increase along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter.The proposed parallel filters uses normal adders (full adder and ripple carry adder) that take more time to execute the program.Therefore, we replaced Ripple Carry Adder (RSA) with Carry Save Adder (CSA) and finally presented the comparison between the timing delays with RSA and CSA.Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolutions from the existing FFA parallel FIR filter, especially when the length of the filter is large.All the simulations observed in modelsim6.4bsimulator, synthesis by Xilinx ISE tool.