High Performance Systolic Architecture by Evolutionary Design
Dept. of Electronics & Communication Engineering,, Hanumanthareddy P S · IOSR Journal of VLSI and Signal processing · 2014
This paper focuses on design of systolic architecture and by the application of evolutionary programming to achieve 100% HUE (Hardware Utilization Efficiency) for space representation containing delays in systolic design.Heuristic method involves EP (Evolutionary Programming) to solve the problems where the solution is in large search space.Using EP, we are able to find the number of different solutions for designing the systolic architecture for regular iterative algorithms.From which the user can choose any design of his choice according to his application.