Logic synthesis strategy based on BDD decomposition and PAL-oriented optimization
Adam Opara, Dariusz Kania · AIP conference proceedings · 2015
A new strategy of logic synthesis for PAL-based CPLDs is presented in the paper. This approach consists of an original method of two-stage BDD-based decomposition and a two-level PAL-oriented optimization. The aim of the proposed approach is oriented towards balanced (speed/area) optimization. The first element of the strategy is original PAL-oriented decomposition. This decomposition consists in the sequential search for an input partition providing the feasibility for implementation of the free block in one PAL-based logic block containing a predefined number of product terms. The presented non-standard decomposition provides a means to minimize the area of the implemented circuit and to reduce of the necessary logic blocks in the programmable structure. The second element of the proposed logic synthesis strategy is oriented towards speed optimization. This optimization is based on utilizing tri-state buffers. Results of experiments prove that the presented synthesis strategy is especially effective for CPLD structures, which consist of PAL-based logic blocks containing a low number of product terms.