Efficient design and implementation of permutation algorithms on the memory hierarchy.
Leonard F. Wisniewski · 1996
For many scientific applications, the data set cannot entirely fit in main memory. The data must reside out-of-core, i.e., on parallel disks. For many basic data-movement operations such as permuting, if the programmer does not design efficient algorithms for accessing data on the parallel disks, the penalty can be quite severe. As processor speeds increase more rapidly than disk speeds, additional disk accesses become even more costly in a relative sense. In this thesis, we focus on efficiently performing the data movement for permutations when the data reside out-of-core. We present a unified approach for performing bit-matrix-multiply/complement (BMMC) permutations at different levels of the memory hierarchy. Our unified approach uses a linear-algebraic technique to decompose an arbitrary BMMC permutation into a number of permutations which we know how to perform efficiently. We show that this technique is flexible enough to apply at the following levels of memory abstraction: parallel disk access, interprocessor communication on distributed memory multiprocessors (with the processors connected by either a mesh or a multistage network), uniprocessor memory access, and the design of combinational circuits. The BMMC permutations include commonly used permutations such as matrix transposition, bit-reversal permutations (used in performing FFTs), vector-reversal permutations, hypercube permutations, matrix reblocking, and permutations used by fast cosine transforms (FCTs). This thesis presents additional work at the parallel disk level of abstraction. We define in-place algorithms for permuting out-of-core data and show how to efficiently perform BMMC, mesh, and torus permutations in place. We also define an application user interface (API) for performing parallel data accesses in the manner suggested by Vitter and Shriver's Parallel Disk Model (PDM).