An EG-LDPC Based 2-Dimensional Error Correcting Code for Mitigating MBUs of SRAM Memories
Ahmet Turan Erozan, Enver Çavuş · 2015
In this paper, a 2-D error correction code architecture based on EG-LDPC and single parity check (SPC) code is proposed as a solution to MBU problem of SRAM memories. EG-LDPC codes have better multiple error correction and detection capabilities than conventional codes and they have low complexity decoders. Therefore, they are suitable for fault tolerant memory applications. The proposed architecture uses (15, 7, 5) EG-LDPC as row encoding and SPC code for column encoding. In order to minimize decoding complexity of 2D structure, a standard array decoder is utilized. The investigated architecture is compared with previously proposed Matrix code method. The proposed architecture is able provide over 95% error correction coverage up to 4 errors and a significant 100% error detection up to 12 bit errors. In terms of MTTFs, the proposed approach achieves 63% improvement over Matrix codes at fault rates of 10-4 and 10-5. Matrix codes and the proposed architecture are implemented using Xilinx XC6SLX16 FPGA and comparison results in term of implementation complexity are provided.