Reconfigurable Area and Speed Efficient Decimator using DA Algorithm
Rajesh Mehra, Lajwanti Singh · International Journal of Computer Applications · 2013
In this paper, an efficient FPGA implementation of a multipliers less decimator is presented for wireless application.DA has been used to implement a decimator taking advantage of embedded LUT based structure of FPGAs.Speed and area efficient solution is designed using half band polyphase decomposition FIR structure.The proposed decimator has been designed with MATLAB and synthesized with Xilinx synthesis tool (XST)10.1 and implemented on Spartan-3E based 3s500efg.320-4FPGA device.Improvement of 28% in speed and 50% in area has been observed as compared to MAC based approach.