Design of Low Power 5T-Dual Vth SRAM-Cell
Chetna Mr. Abhijeet · IOSR Journal of Engineering · 2012
Semiconductor memories are most important subsystem of modern digital systems.In new era the scaling of silicon technology has been ongoing, due to scaling large memory can be fabricated on a single chip as results memories are capable to store and retrieve large amount of information at high speed.But due to high density, power dissipiation gets increases and speed decreases.So there is need for the design of low power and high speed circuit in memory.This paper presents a 5-transistor dual voltage SRAM cell intended for the advanced microprocessor cache market using 1.8v/0.18umcmos technology.The goal is to reduce the power of the cache memory array while maintaining competitive performance.Various existing technologies are briefly discussed with their strengths and weaknesses.The design metrics for the 5-transistor cell are discussed in detail and performance and stability are evaluated.Finally a comparison is done between 6-transistor technology and the 5-transistor technology using dual Vth technique.