Design of BIST with Low Power Test Pattern Generator
V Kirthi, Dr.G.Mamatha Samson · IOSR Journal of VLSI and Signal processing · 2014
In this paper, low power built-in self test (BIST) is implemented for 32 bit Vedic multiplier.The objective of this work is to reduce power dissipation in BIST with increased fault coverage.Various methods of pattern generation are compared keeping in view of power consumption.In this test pattern generation the seed value is changed every 2 m cycles.For this purpose m bit binary counter & gray code generator is used.Signature analysis is done with the help of Multiple input Signature Register (MISR).The signature of MISR will indicate whether the circuit under test (CUT) i.e Vedic multiplier is faulty or not.The results are tabulated and compared.From the implementation results, the low power BIST shows better power reduction than other methods.Simulation is carried out in Xilinx ISE and the design is implemented using Vertex 5 Field Programmable Gate Array (FPGA).