Development of Verification Environment for AXI Bus Using SystemVerilog
Chen Xu, Zheng yu Xie, Xin’an Wang · International Journal of Electronics and Electrical Engineering · 2013
System-on-a-Chip (SoC) design has become more and more complexly. How to verify a design effectively has become a serious challenge. In this paper, how to build up the effective verification environment of AXI using SystemVerilog is introduced. Firstly, the design under verify (DUV) AXI bus is introduced. Then a comprehensive analysis of the verification plan has been made according to the protocol. The proposed integrated verification environment with Functional coverage, score-boarding, assertions and constrained random vectors generation is implemented. With this environment, a high coverage and less time spending verification has been achieved.