An Area efficient and more accurate DA-based DCT with more compression rate
Ashok Kumar Gulla, K. Rajasekhar · IOSR Journal of VLSI and Signal processing · 2012
In this paper, a scheme for the design of pipeline architecture for a real-time computation of the 2-D DCT has been presented.The objective has been to achieve a low computation time by maximizing the operational frequency and minimizing the number of clock cycles required for the DCT computation, which, in turn, have been realized by developing a scheme for enhanced inter-and intra stage parallelisms for the pipeline architecture.it is most efficient to map the overall task of the DCT computation to only two pipeline stages, i.e., one for performing the task of the level-1DCT computation and the other for performing that of all the remaining decomposition levels.In view of the fact that the amount and nature of the computation performed by the two stages are the same, their internal designs ought to be the same.There are two main ideas that have been employed for the internal design of each stage in order to enhance the intra stage parallelism.The first idea is to decompose the filtering operation into two subtasks that operate independently on the evenand odd-numbered input samples, respectively.This idea stems from the fact that the DCT computation is a twosub band filtering operation, and for each consecutive decomposition level, the input data are decimated by a factor of two.