PERFORMANCE MAPPING OF K-LUT BASED FPGAS
Ion I. Bucur · 2007
Circuitele FPGA sunt tot mai mult utilizate in cele mai diverse aplicatii: pentru prototipare rapida a produselor noi (inclusive implementarea rapida a ASIC), pentru emularea logica, pentru producerea uni lot mic de produse, ori daca un dispozitiv trebuie sa fie, in uz, reconfigurabil (calcul reconfigurabil). A determina daca o funcţie, posibil mare, poate fi implementata printr-un bloc logic programabil, din nefericire, este in general, o problema dificila. Aceasta problema este numita problema potrivirii Boole-ene. Lucrarea de faţa introduce implementarea unui nou algoritm menit sa implementeze orientat spre viteza reţele combinaţionale utilizand FPGA-uri bazate pe k-LUT. FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map for performance combinational networks using k-LUT based FPGAs.