Standard Cell Library Design and Characterization using 45nm technology
Prof. Poornima H S, Prof. Poornima H S, Prof Chethana K S · IOSR Journal of VLSI and Signal processing · 2014
Producing designs based on sub-micron technologies at a competitive cost has always been a challenge for the manufacturers.Different Integrated Circuit (IC) implementation approaches have been adopted to reduce the design time and improve manufacturing costs.One of the methods is to use a 'Cell-Based' IC implementation approach using Standard Cell Libraries However, the cost associated with the design or purchase of Standard Cell Libraries (Non-Recurring Expense (NRE)) has been increasing consistently with the shortening of device technology.In this paper we present the development of submicron CMOS Standard Cell Library that is suitable for 45nm CMOS process The intent was to generate a comprehensive library containing core number of necessary cells, providing detailed layout and transistor-level schematic views of every cell, with characterization under the 45nm process, in order to utilize them as a fully synthesizable library.The library is designed using Cadence.