A Programmable Video DSP Architecture for HDTV Applications
Takao Yamazaki, A. Hashiguchi, Masuyoshi Kurokawa, Kenichiro Nakamura, Hiroshi Okuda, Seiichiro Iwase · 1996
This paper describes a programmable DSP for real-time HDTV signal processing. The SIMD architecture with 4320 processor elements operates at 50 MHz with a peak performance of 216 GBOPS (Giga Bit Operations per Second). The single chip DSP can be used for various HDTV applications such as for noise reduction, color space conversion and format conversion (HDTV to/from NTSC).