From Verilog to Bluespec: Tales of an AES Implementation for FPGAs
Omar Choudary · 2010
In this paper I present a combined Verilog and Bluespec implementation of the Advanced Encryption Standard (AES) for FPGAs. This solution relies on the fastest AES implementation for FPGAs, presented by Drimer et al. Bluespec is a versatile HDL, allowing an easy parametrization of a large design. Based on this property I show the simple use of two different AES implementations (AES32 and AES128) in a large Bluespec design. Using the Altera DE2 board and Quartus software I synthesize the design and test it on a Cyclone II FPGA. I present the performance results obtained from several tests and I compare them against the results presented by Drimer et al. The source code for the complete design is made publicly available.