Low cost reorder buffer for MDF FFT with reduced memory size
Chao Wang, Yuwei Yan · 2014
This paper presents a general low cost architecture of reorder buffer for multipath delay feedback (MDF) FFT processor. Because of its high throughput, the MDF FFT is widely adopted in communication systems such as ultra-wideband (UWB), wireless personal area network (WPAN) and long term evolution-advanced (LTE-A). However, as its parallel nonstop output is in bit-reversed order, an output reorder buffer is always required to change it to normal order. The memory of the traditional ping-pong buffer scheme, whose size is twice of the FFT length, takes up the most area of the reorder buffer. To save memory, a new addressing method is proposed where the simultaneous read and write operation use the same set of address. So that only a single RAM bank is required and the total memory size is reduced to 50% of the ping-pong buffer. Mathematical derivation of the single-RAM-bank reorder algorithm and a quantitative express of the area of memory saved by this technique are given. To demonstrate the benefits of this approach, this paper presents a realization of a reorder buffer designed for an 8-path 512-point MDF FFT processor using Silterra 0.13 um process. The core area of the whole output reorder buffer is 0.1 mm2, 95% of which is occupied by RAMs, and 32% of that is saved by this new reorder architecture.