Performance and area aware replacement policy for GPU architecture
Fatemeh Kazemi HassanAbadi, Saeed Safari · 2014
Recent studies have shown that cache partitioning is an efficient technique to improve throughput in multi-core processors. The existing cache partitioning algorithms assume Least Recently Used (LRU) as underlying replacement policy. We propose old Tree-based PLRU on two-level caches with higher speed up or performance matching of LRU at GPUs. The algorithm is based on Pseudo LRU that uses binary tree to reduce area overhead. Also, it uses set-dueling to dynamically adapt its insertion and promotion. We evaluate effect of this policy on both L1 and L2 caches in GPUs. We propose a high accuracy profiling logic and a cache partitioning hardware for our scheme. We evaluate the hardware costs in terms of performance, miss rates, DRAM locality, area, energy, and compare them with LRU and FIFO partitioning algorithms. We define a set of machine models to discuss our scheme on some general purpose workloads. The results show that our solutions impose negligible performance degradation comparing LRU. Then, we use insertion and promotion vectors to compensate for drop of performance. On compute workloads, the technique reduces L2 miss rate about 10.11%.