Stretching the Edges of SVM Traffic Classification With FPGA Acceleration
Tristan Groléat, Matthieu Arzel, Sandrine Vaton · IEEE Transactions on Network and Service Management · 2014
Analyzing the composition of Internet traffic has many applications nowadays, like tracking bandwidth-consuming applications or QoS-based traffic engineering. Even though many classification methods, such as Support Vector Machines (SVMs) have demonstrated their accuracy, the ever-increasing data rates encountered in networks are higher than existing implementations can support. As SVM has been proven to provide a high level of accuracy, and is challenging to implement at high speeds, we consider in this paper the design of a real-time SVM traffic classifier at hundreds of Gb/s to allow online detection of categories of applications. We show the limits of software implementation and offer a solution based on the massive parallelism and low-level network interface access of FPGA boards. We also improve this solution by testing algorithmic changes that dramatically simplify hardware implementation. We then find theoretical supported bit rates up to 473 Gb/s for the most challenging trace on a Virtex 5 FPGA, and confirm them through experimental performance results on a Combov2 board with a 10 Gb/s interface.