Performance Analysis of Minimum Hop Source Routing Algorithm for Two Dimensional Torus Topology NOC Architecture under CBR Traffic
Dinesh Lekariya · IOSR Journal of Electronics and Communication Engineering · 2013
Network on Chip has emerged as new paradigm for the system designers to design an on chip interconnection network.However, NOC presents a large amount of array of design parameters and decision that are sometimes difficult to tackle.Apart from these issues NOC presents a framework of communication for complex SOC and has been widely accepted by the industries and academia's.Today all the complex VLSI circuitry which requires an on chip communication between them are the part of NOC.The mature concepts of communication network such as routing algorithm, switching technique, flow and congestion control etc in the NOC are the important features on which the performance of NOC depends.This paper introduces the efficient source routing algorithm which generates the minimum hop from source to destination.Performance of NOC network in terms of latency and throughput for minimum hop source routing algorithm is also evaluated.