An Average Response Computer Using Delay Line Memory
Takayoshi Totani, Toshihiro Kawashima · Transactions of the Society of Instrument and Control Engineers · 1972
This paper describes the design principle and the construction of a simple average response computer which uses a wire delay line memory as an accumulator. A series of rectangular pulses or the maximum-length binary sequence is used for an input signal to the measured system. In the case of the maximum-length binary sequence input, the response of the system is computed and summed up into the accumulator by making use of a fast m-sequence signal which is synchronized with the cycle time of the delay line. The computed response consists of the increments of the step response of the system within the sampling interval. The minimum sampling interval of this device is 40μs.The rms errors of the averaged response are analyzed under the condition that the noise is additive and the system is linear. The rms error obtained with the rectangular pulse input is compared with that obtained with the m-sequence input. It is concluded that the m-sequence input is extremely effective from the point of view of the measuring time when the noise level of the system is high and the amplitude of the input signal is restricted within some limit. An experimental example which shows the effectiveness of the m-sequence signal input is also presented.