Wait-Free Message Passing Protocol for Non-coherent
Isa ́ ias · 2012
The number of cores in future CPUs is expected to increase steadily. Balanced CPU designs scale hardware cache coherency func- tionality according to the number of cores, in order to minimize bottle- necks in parallel applications. An alternative approach is to do away with hardware coherence entirely; the Single-chip Cloud Computer (SCC), a 48 core experimental processor from Intel labs, does exactly that. A wait- free protocol for message passing on non-coherent buffers was introduced with the RCKMPI library, in order to support MPI on the SCC. In this work, the message passing performance of the protocol is modeled. Ad- ditionally, a port for symmetric multi-processors is introduced and used for comparison with MPICH2-Nemesis and Open MPI. Performance is analyzed based on statistics collected on a 4-dimensional space composed of source rank, target rank, message size and frequency.