Boundary-scan test circuit designed for FPGA
Xiaojun Ma, Tong Jiarong · 2003
Boundary scan is a widely adopted DFT (design for test). According to the characteristic of FPGA application, this paper presents a boundary scan circuit designed for FDEGA (field-programmable datapath enhanced gate array), an FPGA new architecture of our group. The design emphasizes the function of PCB level test while considering chip level test function as well. We also integrate device-programming function into the circuit. In implementation of our design, single DFF (D flip-flop) chain structure is adopted to decrease area consumption. We finished the layout design in 0.6mm CMOS process and integrated it into our FDEGA chip. Test results of fabricated chip meet the design requirement, and shows that the circuit can achieve the expected test function and programming function while observing IEEE1149.1 standard.