Unified Automated System Level Test Bench to Verify DDR2/3/4 and LPDDR2 Memory Controllers - Layered
Javagal Nagaraja Raghavendra · ECS Transactions · 2013
This paper aims at discussing in architecting a Generic Infrastructure for an Automated Layered Test Bench to verify DDR2, DDR3, DDR4 and LPDDR2 memory controller design independently in compliant with Open Verification Methodology (OVM) guidelines. This environment while satisfying the horizontal/vertical re-usability can be configured to verify each memory standard independently and across the projects with configurable user interfaces such as AXI, XILINX Custom interfaces (User Interface / Native Interface) in a plug-play fashion. This paper also aims at the effective usage of SV constructs and OVM built in features like Parameterized classes, OVM configuration mechanism, Macros, Reporting Mechanism which are used to build a Re-usable automated and layered system level test bench to be used across a set of technologies and projects.