4-Input Decimal Adder Using 90 nm CMOS Technology
Meena Aggarwal · IOSR Journal of Engineering · 2013
The core of every microprocessor, digital signal processor (DSP), and data processing application-specific integrated circuit(ASIC) is its data path.At the hearts of data paths and addressing units are arithmetic units, such as a comparators , adders, and multipliers.In this paper, a 4-input decimal adder has been developed using 90 nm CMOS technology.The schematic of decimal adder is designed and simulated for its behavior using DSCH-3.1The layout of simulated adder is created using Verilog based netlist file which is further simulated using Micro wind 3.1 to analyze the performance.The result shows that designed decimal adder has consumed 0.603mW power.