A spacecraft test strategy - From silicon to system with boundary scan
Brian Stearns · 16th International Communications Satellite Systems Conference · 1996
Spacecraft electronics are rapidly following the same trends as electronics in commercial systems: higher printed circuit board density and tighter lead spacing due to newer advanced electronic packaging. These two issues alone are serious enough that system Test and Integration engineers are working closer with design engineers to ensure the system can be tested without considerable investment in capital equipment or significant schedule delays. A comprehensive test strategy initiated as early into the design cycle as possible can yield significant improvement in test coverage, faster fault diagnosis, lowered test and development costs, shorter system development time, and faster time to market. The IEEE 1149.1 Standard for Boundary Scan Test was developed to address the physical access issues created by advanced digital electronics packaging and dense/complex printed circuit board designs. Designing the system electronics with Boundary Scan not only supplements existing test strategies, but also enhances system performance and offers significant value to system users by minimizing downtime. This paper examines the use of the 1149.1 Standard as a tool to integrate spacecraft electrical test from silicon to the board, as well as a possible method to extend the standard to the module and system level for a comprehensive test strategy which covers the entire system life cycle. Introduction Compared with the expensive infrastructure needed to support ground-based distribution systems, space and spacecraft are now proving to be the more cost-effective communications medium. The result is an explosive growth in demand for space services and a more competitive communications space market. Manufacturers of space-based communications systems find they are confronted with stiff competition as the number of systems suppliers increases to meet this burgeoning demand. In the past, satellite assembly projects were completed in the back of a laboratory, one at a time, by several scientists over 2 to 5 years, with designs intended for one-time application. Today, standardization and re-use are design objectives. Rather than projects requiring a single system in orbit, today's development projects and concepts are supported with 12, 24, 66, and up to 840 systems in a constellation of satellites. In order to manufacture this quantity of satellites, new approaches are needed to achieve consistent and repeatable processes, high reliability, and throughput in facilities dedicated to cost-effective high volume manufacturing of satellite hardware. Optimizing the production process requires careful consideration of all phases of the production cycle. Product design should support manufacturability and test. New development projects should be approached by cross-functional concurrent engineering teams using Design for Manufacturability and Design for Testability (DiT)'. Significantly reduced time to market is achieved by focusing on the Integration, Test and Validation phases of the production cycle, which can consume from 25-50% of the schedule. With careful planning and parallel development efforts against well understood and documented objectives, significant cycle time improvements and cost reductions will result. Test Methodologies A test strategy verifies that previous steps (design, fabrication) were done correctly and verifies performance requirements. By first dividing the test into categories of design and process, then into subcategories of structural, functional, parametric, and performance, detailed objectives can be written for each and a well-defined test strategy developed. A structured approach to test is also critical. All disciplines of the project should follow a standard set of guidelines for a consistent approach across subsystems and for a hierarchical approach across integration levels. Traditional test methods for digital electronic printed circuit board (PCB) assemblies use several techniques. Most commonly they are some combination of access-to-test points that use edge connectors for functional test and special test jigs using spring loaded pogo-type pins for in-circuit 1344 *AIAA Member Copyright © 1996 by the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.