Resource-Speed Trade-Off of the SHA-1 Algorithm Implementation in Low Cost SRAM-Based FPGA
Jianhua He, Hu Chen, Huaqiang Huang · ASME Press eBooks · 2009
In the typical implementation of the SHA-1 algorithm, resource constrain makes it meet the limit in the low cost FPGA. The huge need of Slice challenges the use of it. In this paper, we present a spectrum of approaches to implement SHA-1. They are not only taking full advantage of the embedded block RAM and distribute RAM in the FPGA, but also the algorithm optimization to balance the logic block consumption and the speed. We aim to provide different implementation to satisfy the FPGA of different classes in various embedded applications.