Optimization of Adaptive Fir Filter for High Throughput, Low Power & Area Using Distributed Arithmetic
K Kalaiarashi, Mr.Santhakumar.K Kalaiarashi.K · IOSR Journal of VLSI and Signal processing · 2014
This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA).The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations.The DA-based inner-product computation by conditional signed carrysave accumulation is replaced with CSA Binary to Excess-1 Converter (BEC) in order to reduce the sampling period and area complexity.Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations.It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design.