Designing of BIST Architecture of Generic Multipliers
Anju Rajput · IOSR Journal of VLSI and Signal processing · 2014
The aim of this paper is to present the BIST architecture of generic multipliers.The generic architecture of all the four multipliers i.e. array, column bypass, wallace tree and booth multiplier has been designed .The verification of all these four different multipliers has been done by using BIST controller.The LFSR (linear feedback shift register) has been designed, which will generate the automatic inputs.Then the BIST controller has been designed which will check these multipliers by using input patterns obtained from LFSR.BIST controller will verify these four generic architectures whether they are faulty or not By using it, the logics or design of these multipliers need not to be verified by any other means.This is the advantage of this design that it does not require third party verification.The simulation has been carried out on ModelSim (Student Editon) EDA tool 10.0c and synthesis has been carried out on ISE Design Suite 14.4.