A New Memory Reduced Radix-4 CORDIC Processor For FFT Operation
A. Yasodai · IOSR Journal of VLSI and Signal processing · 2013
A complex number can be interpreted as a vector in imaginary plane.The vector rotation in the x/y plane can be realized by rotating a vector through a series of elementary angles.These elementary angles are chosen such that the vector rotation through each of them may be approximated easily with a simple shift and add operation, and their algebraic sum approaches the required rotation angle.This can be exercised by CORDIC ('CO-ordinate Rotation Digital Computer) algorithm in rotation mode.In this paper, we have proposed a pipelined architecture new memory less z-path eliminated CORDIC algorithm for FFT computation.Pipelined architecture by pre computation of direction of micro rotation, radix-4 number representation, and the angle generator has been processed in terms of hardware complexity, iteration delay and memory reduction.Comparison of the proposed architecture with the conventional radix-4 architectures is elaborated.The proposed algorithm also exercises an addressing scheme and the associated angle generator logic in order to eliminate the ROM usage for bottling the twiddle factors.It incorporates parallelism and pipe line processing.The latency of the system is n/2 clock cycles.The throughput rate is one valid result per eight clock cycles.Additionally VLSI implementation on Virtex -4 FPGA is done.The implemented design operates at 450.654 MHZ of clock rate with a power consumption of 175.90mW.