Designing one-bit Full-Adder/Subtractor based on Multiplexer and LUT��s architecture on FPGA
TranBichThuan Pham -, Yi Wang, Renfa Li · International Journal of Digital Content Technology and its Applications · 2013
TranBichThuan Pham, Yi Wang, Renfa Li College of Information Science and Engineering, Hunan University, ChangSha, Hunan, China. [email protected], [email protected]. Faculty of Electronic and Communication technology, Industrial University of Hochiminh City, HoChiMinh, Vietnam. [email protected]. Dept. of Electrical and Computer Engineering, National University of Singapore, Singapore.