Speed-energy considerations of microprocessors and APU's for tactical missile applications
K. L. Grundy, Несин Даниил Юрьевич · 1979
Interface f eatures of a CMOS microprocessor and an arithmetic processing unit (APU) are described in relation to tactical missile applications. Power switching to the APU minimizes energy consumption. Software examples and methodologies are discussed. An energy analysis shows an APU augmented CPU system has the potential of reducing the energy to perform a software task by a factor of 7:1, while reducing the solution time by a factor of 200. Reduced memory size and usage in the APU-CPU pair type of architecture is displayed as an important consideration in power conservation for tactical applications of microprocessors.