An efficient motion estimation hardware architecture for MPEG-4 binary shape coding
Daniel Larkin · 2005
This paper tackles the problem of accelerating binary motion estimation for MPEG-4 binary shape coding. In addition, the proposed architecture attempts to reduce power consumption and silicon area. The solution exploits redundant operations in the bit counting (BC) calculation, by a mechanism known as early termination. Further data redundancies are exploited by using a run length coding addressing scheme, where only pixels which contribute to the final BC value are accessed. By using these two techniques throughput is increased and only relevant memory is accessed. Two low-power, fast exhaustive binary block-matching motion estimation architectures are presented.