Design and Implementation of Area and Power Optimised Novel Scanflop
R. Jayagowri, K. S. Gurumurthy · International Journal of VLSI Design & Communication Systems · 2011
The power consumption of IC during test mode is higher than its normal mode.This brings the power as one of the major design constraints for today's low power design technologies.In normal scan based test circuits most of the power consumed due to the switching activity of scanflops during shift and capture cycles.In this paper a novel scanflop is presented which reduces the switching activity of the scanflop for clock and it reduces the power consumption of the circuit and it also reduces area and test time too.The proposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bits of test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during its data mode.The design and functionality of the proposed scanflop is discussed and compared with the different flipflops which shows that the proposed scan flop reduces the test time and clock switching activity by 50%, area by 30% and static power by 25%.