A Buffer Cache Algorithm Using the Characteristic of Mobile Applications based on Hybrid Memory Architecture
Chansoo Oh, Dong Hyun Kang, Minho Lee, Young Ik Eom · 2016
In general, current mobile devices employ a buffer cache mechanism which has been designed to mitigate the performance gap between CPU and storage. However, it cannot fit in mobile devices because it does not consider the characteristics of the mobile applications (e.g., foreground or background state). Therefore, existing buffer cache mechanisms can cause performance degradation by I/O interference between foreground applications and background applications. In addition, DRAM accelerates energy consumption by performing periodic refresh operations. Therefore, DRAM-based memory system can cause critical power problem due to its limited battery capacity in the mobile devices. In this paper, we propose a novel buffer cache algorithm for mobile devices based on hybrid memory architecture composed of DRAM and non-volatile PCM. Proposed algorithm is based on key observation that background applications rarely issue I/O requests and they may interfere with foreground applications. For evaluation, we implemented the proposed algorithm and compared the performance with two widely known algorithms. Our experimental results show that our algorithm reduces the elapsed time of the foreground applications by 70% on average and the power consumption by 67% on average while operating same workloads.