VLSI Architecture of Kalman Filters with Minimum Latency Based on FADDEEVA Algorithm
Yoshitaka Tsunekawa, Kyo Takahashi, Mamoru Miura · Transactions of the Society of Instrument and Control Engineers · 1998
In this paper, we propose VLSI architecture of Kalman Filters with minimum latency based on FADDEEVA algorithm. It is important to minimize latency, because latency degrades a stability of feedback systems. In proposed architecture, the minimization of latency is achieved by parallel computation of parameters of Kalman Filters and the triangularization and nullification process of the FADDEEVA algorithm. This architecture has a highly parallel structure. For an n state and m measurement dynamic system, this architecture requires latency of only (3+m+6⌈log2n⌉)tas+(6+m)tm+td, where tas, tm and td indicate delay of an adder, a multiplier and a divider, respectively. This means a reduction of latency of approximately 0.06 times when compared to a systolic array Kalman filters for the filter order of m=n=100. Moreover, latency of this architecture slightly increases against the increasing filter order, so that this architecture is also effective to the higher order Kalman filters. The proposed architecture is very suitable for VLSI implementation, because it can be simply constructed from six kinds of modules and some basic arithmetic elements.