A REVIEW ON GLITCH REDUCTION TECHNIQUES
Vikas · International Journal of Research in Engineering and Technology · 2014
This paper presents different techniques for reducing glitch power in digital circuits.The aim of this study is to minimize glitch power as glitch power comes under dynamic power, so that power dissipation will reduce up to some extent in digital circuits.Warren Shum et.al [2011] work shows glitch power in FPGA's varies from 4 % to 73 % of total dynamic power having an average of 22.6 %. Warren Shum et.al [2011] and J. Lamoureux et.al [2008] motivates us to reduce glitch power in digital circuits as well as FPGA's.Different techniques are available for reducing glitch power like gate sizing, gate freezing, multiple threshold transistors, hazard filtering, balancing path delay, by reducing switching activity etc.