Optimized Contact Engineering to Maximize Cell Current in NAND Flash Memory Technology
Joong Ho Yoon, Hong-Sig Kim, Yung Sam Kim, Jun Kyoung Lee, Eui Sung Han, Yeon-Un Jeong, Young Ik Lee, Sung Jin Jang, Hyun Gil Kim, Sung Wook Park, Sae Hui Park, Haebum Lee, Kyupil Lee, In-soo Cho · ECS Transactions · 2013
In this research we have confirmed that Nand flash cell current increases by optimization of contact barrier metal (BM) deposition and plug implantation (IIP) doping condition, which result in improved contact resistance (Rc) and cell leakage. Plug IIP dopant, BF2, which has been applied to P-type Transistor (Tr) for lowering Rc sacrifices contact process margin in cell area of n-type occurred by cell leakage. We could dramatically improve P-type Contact Rc and contact process margin by lowering BM deposition process temperature and adopting plug IIP doping with phosphorous (Ph.) respectively