Designing Of Pipelined Architecture of Arithmetic Core and Analysis of Area and Timing Performance
Hemraj Sharma, Abhil asha · IOSR Journal of VLSI and Signal processing · 2014
The aim of this paper is designing of pipelined architecture of arithmetic core and analysis of area and timing performance of that arithmetic core consisting of fixed point as well as floating point arithmetic cores.The basic concept behind designing such a core is to optimally utilize the algorithms of fixed point as well as floating point arithmetic operations, i.e., addition, subtraction division and multiplication and to enhance the operational speed of these calculations along with comparing a better technique out of fixed and floating point techniques to choose one of them for implementing in future.For this purpose, the arithmetic core is divided into two parts, namely, fixed point arithmetic core and floating point arithmetic core.Both the fixed point as well as floating point cores are sub-divided into four parts which are basically the mathematical operations, i.e., addition, subtraction, multiplication and division.In this Research paper, we discuss the fixed point arithmetic core.The simulation has been carried out on Modelsim (Student edition) EDA tool 10.0c.