Enhancing Multiplier Speed in Fast Fourier Transform Based on Vedic Mathematics
Meenaakshi Sundari, D Subathra, Dhanalaxmi M.S · International Journal of VLSI Design & Communication Systems · 2013
Vedic mathematics is an ancient system of mathematics which has a unique technique of calculations based on 16 sutras.The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam Navatashcaramam Dashatah, and Anurupye Vedic mathematical algorithms.These algorithms gives minimum delay and used for multiplication of all types of numbers.The performance of high speed multiplier is designed and compared using these sutras for various NxN bit multiplications and implemented on the FFT of the DSP processor.Anurupye sutra on FFT is made efficient than Urdhva tiryabhyam and Nikhilam Navatashcaramam Dashatah sutras by more reduction in computation time.This gives the method for hierarchical multiplier design.Logic verification of these designs is verified by simulating the logic circuits in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL coding.