A fault-tolerant routing algorithm in 3D topology manycore processors
Morteza Fathi, Sara Ebrahimi, Hossein Pedram · 2015
The unprecedented progress in semiconductor technology has provided great opportunities for commercialized computationally intensive applications. Amdahl's law was applied for multiprocessor computers till several years ago but his laws are now useful to help us understand and develop using manycore chip multiprocessors (CMP). Obviously manycore-based designs could not be done blindfold and it needs detailed calculations. In CMP's with hundred processing cores, 3D topology in the form of network-on-chip (NoC) can be used for shortening the wires length leads to low latency, low power dissipation and scalability. Meanwhile faults can occur in NoC both at the router and in communicational links. There are many fault-tolerant solutions that their function is based on rerouting the packets. In this paper we propose a fault-tolerant technique which is completely adaptive and use available non-broken links. The focus of this technique is keeping the performance of NoC when there is a faulty link and the packets from a source to a destination never get lost. Experimental results shows that this algorithm can tolerate more than 10 faulty links in different parts of NoC and it can achieve more than 97% reliability.