High-Level Data Flow Description of FPGA Firmware Components for Online Data Preprocessing
H. Engel, F. R. Grull, U. Kebschull · GSI Repository (German Federal Government) · 2014
FPGA firmware for detector read-out is commonly described with VHDL or Verilog.Data processing on the algorithmic level is a complex task in these languages and creates code that is hard to maintain.There are high level description frameworks available that simplify the implementation of processing algorithms.A sample implementation of an existing algorithm and the comparison with its VHDL equivalent show promising results for future online preprocessing systems.Field Programmable Gate Arrays (FPGAs) are widely used in high energy physics detector read-out chains due to their flexibility.The protocols and interfaces are usually implemented with hardware description languages like VHDL or Verilog.With FPGAs getting bigger and faster they become more and more suitable for performing complex data processing tasks.This can reduce the data volume and significantly ease demands on later software based processing steps.The drawback of the commonly used hardware description languages is that they are mostly working on the Register Transfer Level.This is perfect for high performance protocol and low level interface implementations.However, using these languages to implement data processing on an algorithmic level requires experienced developers and usually involves customized IP cores and latency matching of components.This creates a rather complex and static design.There are several high level hardware description frameworks available that provide their own languages to describe data processing steps on an algorithmic or data flow level.Some of them also come with an own framework including building blocks for PCIe or DRAM interfaces.This significantly speeds up the development compared to a description in plain VHDL or Verilog.The underlying framework of this work is made by Maxeler Technologies.The platform generates a pipelined version of the algorithm after its data flow graph has been described in a Java-like programming language [1].The compiler manages the scheduling of the design, inserts latencies in the generated pipelines wherever needed to keep the data in sync, and instantiates interfaces to PCIe or DRAM if required.A software environment with a device driver and C API provides easy to use stream interfaces to the hardware.The compiler translates the data flow description into VHDL code which is then run through the vendor tools.The algorithm described in this way is the FastClus-terFinder that was used as a VHDL core in the readout of the ALICE Time Projection Chamber during LHC run pe- * Work supported by HGS-HIRe, HIC4FAIRChannel Decoder Channel Mapping Channel