Design and Implementation of High Speed II Rand FIR Filter using Pipelining
Ravinder Kaur, Ashish Raman, Hardev Singh, Jagjit Singh Malhotra · International Journal of Computer Theory and Engineering · 2011
The FIR & IIR Filters are being designed using HDL languages since speed is among the chief interest in this era; the main objective is to enhance the speed of the system. In the whole system if the speed of the individual block is enhanced the overall speed of the system is enhanced digital computer arithmetic is an aspect of logic design with the objective of developing appropriate algorithms in order to attain an effective utilization of the available hardware. Since ultimately, speed, power and chip area are the most often used measures of the efficiency of an algorithm, there has a strong link between the algorithms and technology applied for its implementation. Here it is done by applying the technique pipelining. The comparative analysis of pipelined & non-pipelined FIR and IIR filters is performed by using different FPGA's. The results reveal that the implemented filters turn in a consistent quality of output.