Storage, retrieval and processing of video
Qiang Li, Radhika S. Grover · 2003
We present the design of a video-on-demand system called Sb torage Abrea network Mbultimedia server (SAM). SAM manages a set of storage devices connected by a storage area network, and can be scaled to service thousands of clients with performance guarantees. The architecture, data layout, admission control scheme and support for interactive operations are described. An inter-node data layout scheme called constrained random striping (CRS) is proposed for SAM. CRS uses a novel placement of the stripe units across nodes that are connected on a logical loop, which reduces the start-up latency of a client. The start-up latency is the smallest time duration for which a client must wait between initiating a new request and starting display, in order to prevent jitter. CRS can provide a reduction of up to about 40% in the start-up latency compared to other placement schemes. SAM provides multi-resolution video to clients with different levels of quality. An intea-node placement scheme called Partial-Bundled is developed for variable bit rate multi-resolution video. This scheme can support from 10% to 100% more clients than other schemes depending on system parameters such as round time. We address the issue of limiting client jitter to within acceptable limits with an admission control scheme. In this scheme, deterministic guarantees are provided for minimum layers of the multi-resolution video, and statistical guarantees are provided for higher layers of multi-resolution video. SAM supports VCR operations such as fast-forward and rewind. We show that the statistical multiplexing of available resources can reduce the resources required to support interactive service on a parallel server. An analytical model is developed to predict the probability with which stream requirements can be met for a given node buffer level. SAM also continues to provide uninterrupted service in the event of a storage device failure in the system. Two heuristic algorithms are proposed to provide for graceful degradation in the presence of disk failure. The heuristic algorithms attempt to maximize the rewards (related to average quality of a stream) while reducing the resolution of clients. Since SAM uses compressed video, it must be processed in video coders and decoders. The basic operation in the discrete cosine transform (DCT) and its counterpart (IDCT), which are used in MPEG coding and decoding respectively, is matrix multiplication. Two ways of implementing matrix multipliers are using Distributed Arithmetic (DA) structures and systolic arrays. We present multiplier designs using serial and parallel DA look-up table and accumulator structures, on Xilinx FPGAs. In these designs, an n-bit carry chain, where n is the word length, is broken into smaller r-bit chains, 1 ≤ r < n. A design space exploration of these designs shows the cost/performance tradeoffs with various carry-chain lengths. A design for a systolic-array based multiplier is also presented. The design procedure is shown in detail by presenting the dependence graph, time and space mappings of the design. We explore d-r DA structures for DCT on Xilinx FPGAs, where d is the digit size and r is the length of the carry chain in the critical path, for 1 ≤ r ≤ n where n is the width of the internal data paths in the design. It is shown that the designs provide a variety of cost/performance trade-offs.