Simultaneous subordinate microthreading.
Robert S. Chappell, Yale N. Patt, Edward S. Davidson · Deep Blue (University of Michigan) · 2004
Tomorrow's ultra-wide microprocessors will be unable to supply enough work from single-threaded programs to take advantage of all available execution resources. Instruction processing bottlenecks, such as branch mispredictions and data cache misses, will combine to limit performance to a fraction of the potential. Simultaneous Subordinate Microthreading (SSMT) is a new paradigm that takes advantage of spare execution resources to improve single-threaded performance. Additional useful work is supplied in the form of microthreads, small routines of instructions that execute simultaneously with the running program, called the primary thread. Microthreads improve the performance of the primary thread by interacting with the microarchitecture to reduce instruction processing bottlenecks. This dissertation presents the SSMT paradigm and demonstrates two applications of SSMT that improve performance by correcting branch mispredictions. The first application, Microthread Hybrid Branch Prediction, uses microthreads as the specialized components of a hybrid branch predictor. The resulting microthread hybrid improves accuracy while bypassing the limitations of a hardware hybrid implementation. The second application of SSMT, Microthread Partial Branch Pre-computation, dynamically constructs microthreads to speculatively precompute branch outcomes along frequently mispredicted paths. These microthreads achieve nearly perfect prediction accuracy and also provide some prefetching benefit. Using either of these two applications of SSMT, performance of the primary thread can be substantially increased. This dissertation also describes the software and hardware changes necessary to support SSMT on a futuristic microprocessor. A set of microthread constraints is specified to simplify the requirements. Using these microthread constraints, an implementation can be achieved that limits additional complexity and has virtually no impact on the primary pipeline. A sensitivity analysis demonstrates that reasonable design points are possible for support of SSMT. Finally, this dissertation examines two inherent problems with the successful use of SSMT: microthread overhead and microthread latency. A number of techniques for limiting overhead and tolerating latency are discussed, including the use of special-purpose microinstructions and dynamic feedback. When applied to Microthread Hybrid Branch Prediction and Microthread Partial Branch Precomputation, these techniques for reducing overhead and latency can sometimes make the difference between performance loss and performance gain.