Interfacing of Systemverilog and Systemc Using Transaction Level Modeling
Prem Kumar Lohani, K Ranjani, Ravishankar Ravishankar, C Sundaresan, C V S Chaitanya · 2014
SystemVerilog and SystemC are extensively used for design and Verification in VLSI industry. This paper propose a method to combine SystemVerilog and SystemC code in a single hardware/software simulation which allows design teams to leverage abstract representations of system function as it increases system simulations speed. This paper also purposes a method of developing generalized Noise Channel Model to mimic the real timing scenarios in communication protocols and provide physical medium timing information to higher layers using SystemC.