Reduction of Leakage Current and Power in Full Subtractor using MTCMOS Technique
M. Saroja, M.Ramamurthy Naik · 2014
In this paper a full subtractor using MTCMOS technique design is proposed. Combinational logic has extensive applications in quantum computing, low power VLSI design and optical computing. Reducing power dissipation is one of the most principle subjects in VLSI design today. But Scaling causes sub threshold leakage currents to become a large component of total power dissipation. Low power design techniques proposed to minimize the active leakage power in nanoscale CMOS very large scale integration(VLSI) systems. Using MTCMOS approach compare leakage current and leakage power of full subtractor in active mode leakage current in conventional full subtractor is 271.1 fA and proposed 2-stack full subtractor in 16 nm technology is 0.528 I¼A, reduction in current is almost 90%. simulation result is performed at 0.9 volt using electric tool for schemantic and LT spice for simulation in 45 nm,32 nm,28 nm and 16 nanometer technology.