Energy Conscious On-Chip Communication Bus Synthesis and Optimization for MPSoC Architectures
Sujan Pandey · Technischen Universität Darmstadt · 2008
Two major trends can be observed in modern system-on-chip design: first the growing trend in system complexity results in a sharp increase of communication traffic on the on-chip communication bus architectures. The second trend in technology scaling indicates that the wires are getting thinner and results in increment of wire delay. These trends, taken together, designing on-chip communication bus architectures is becoming an ever more challenging task for system designers. Thus, the aim of this thesis is to explore several algorithms that synthesize energy efficient on-chip communication buses. The algorithms reduce chip size and power consumption by optimizing the bus widths, the number of buses, and the voltage levels. An assumption for synthesis is that a system has been partitioned and mapped onto the appropriate modules of a multiprocessor system-on-chip (MPSoC) architecture. Based on the partitioned and mapped modules, a communication task graph is extracted to model communication between on-chip communicating modules. The synthesis approach is formulated as scheduling, allocation, and binding problems. Once correctly formulated, these problems are solved with the help of an optimization tool to find the optimal bus width and the number of buses. As the device geometry and the wires are scaled down, a growing number of transistors can be integrated on a single chip, which leads to an increase in power consumption per unit area. This, in turn, results in the degradation of both device reliability and system performance. Thus, it is essential to optimize bus energy consumption during the synthesis of communication buses. As a major contribution, this thesis proposes a simultaneous on-chip communication bus synthesis and voltage scaling technique, that finds a trade-off between communication bus cost (bus width and number of buses) and energy consumption. The slack of each communication task is exploited in order to share communication bus usage and to scale down the bus operating voltages. As the continuous voltage scaling technique delivers an ideal energy consumption characteristics, it cannot be applied for the digital design due to the expensive voltage regulators. To cope with this problem, a heuristic for discrete voltage scaling technique is proposed, which can be solved in polynomial time complexity. In a real-time embedded system, the amount of data to be transferred between on-chip modules is not fixed over time. This is due to the diversity of applications that run on a single chip. Furthermore, as the process technology is scaled down, the effects of process variations are becoming a significant on system performance. In order to incorporate the combined effects of the data size and the process variations on the performance of communication buses, this thesis proposes an extended model for communication synthesis. The proposed model simultaneously performs on-chip communication bus synthesis and voltage scaling under data size and process variations. The problem is relaxed to a nonlinear optimization model, which synthesizes the optimal bus widths and the number of buses considering worst case data traffic and process variations. The experiments conducted on an automatically generated benchmark and real-life applications show that applying voltage scaling during the synthesis of on-chip communication buses effectively reduces dynamic power consumption, leakage power consumption, and mitigates the effects of process variations.