VHDL synthesis of Montgomery modular multiplier
Sarasvathi Thangaraju. · DR-NTU (Nanyang Technological University) · 2005
This work describes the characteristics of two architectures designed to implement modular multiplication using the Montgomery Modular algorithm: the first FPGA design has an iterative sequential architecture while the second has a systolic array-based architecture. The first architecture proposed in this work where Montgomery algorithm was implemented using an iterative design reduces the area usage in detriment of response time while the second architecture where Montgomery Modular Multiplication (MMM) was implemented using the systolic array reduces time response in detriment of area requirement. The speedup in modular computations using systolic array is due to the instantiation of components resulting in parallel computation.