On interfacing HDL to knowledge bases
Peter Francis Klon · 1986
This dissertation examines and demonstrates concepts for an interface between the University of Alabama in Huntsville (UAH) Hardware Expert Synthesis System (UHESS) and the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language System (VHDL) in terms of design data representation. The work presented here utilizes the UHESS-VHDL interface as a vehicle to examine the relational abstractions between design data elements and their semantic representations with respect to synthesis/design type problems. The analysis develops abstractions of design data objects. These abstractions are then applied to the development of a generic hologram representational scheme suitable for use in an expert system knowledge base. The hologram combines the features of prototype and semantic network representations into a single structure that holds both design data and design knowledge. This structure is dual in nature, maintaining both structural and semantic information. Application of the object abstractions and hologram representation to several design problem domains is provided. This representational scheme is demonstrated by means of a simulated UHESS-VHDL interface.