A novel interleaved and distributed FIFO
Santosh Sood · cIRcle (University of British Columbia) · 2010
In deep submicron technologies, the delays of metal lines continue to increase in spite of an increasing number of metal layers and the use of low-k dielectrics. Thus, some form of interconnect pipelining is required in throughput intensive designs. Various approaches have been used for interconnect pipelining, e.g., synchronous, asynchronous, GALS and source-synchronous, and each presents a trade-off between the throughput and latency that can be achieved. This work provides an evaluation of the synchronous and the source-synchronous methods of interconnect pipelining. Reference designs for various synchronous and source-synchronous signalling methods are presented. The source-synchronous method entails the forwarding of a clock along with data; this forwarded clock suffers from skew due to process, voltage and temperature variations along the forwarded path. A FIFO is used to compensate for the skew between the forwarded clock and the local clock at the receiver end. We present a novel, interleaved and distributed FIFO that implements wave pipelining between the FIFO stages. This FIFO design helps to lower the latency of the source-synchronous interconnect. A metric of comparison called velocity is introduced, and a comparison of the performance of synchronous and source-synchronous signalling is presented on the metrics of throughput, velocity and power.